CRISPR Cas/Exosome Based Diagnostics: Future of Early Cancer Detection

Trending and Thriving, CRISPR/Cas has expanded its wings towards diagnostics in recent years. The potential of evading off targeting has not only made CRISPR/Cas an effective therapeutic aid but also an impressive diagnostic tool for various pathological conditions. Exosomes, 30 - 150nm sized extracellular vesicle present and secreted by almost all type of cells in body per se used as an effective diagnostic tool in early cancer detection. Cancer being the leading cause of global morbidity and mortality can be effectively targeted if detected in the early stage, but most of the currently used diagnostic tool fails to do so as they can only detect the cancer in the later stage. This can be overcome by the use of combo of the two fore mentioned diagnostic aids, CRISPR/Cas alongside exosomes, which can bridge the gap compensating the cons. This chapter focus on two plausible use of CRISPR/Cas, one being the combinatorial aid of CRISPR/Cas and Exosome, the two substantial diagnostic tools for successfully combating cancer and other, the use of CRISPR in detecting and targeting cancer exosomes, since they are released in a significant quantity in early stage by the cancer cells

Lubrication Potential of Boron Compounds: An Overview

Boron compounds are emerging as promising materials for Q wide range of applications in automotive and industrial lubrication sys- tems. Several studies conducted on boron compounds have revealed that they exhibit desirable properties for preparing stable and compat- ible lubricant components for a new generation of lubricating oil formulations. Boron-containing lubricants have major tribological ad- vantages, such as antiwear efficiency, good film strength, high- temperature resistance, and self-lubricating properties. The increasing number of patents concerning boron-containing lubricants illustrates commercial interest in this area. Boron lubricants can be used in many forms, such as oxides, esters, and boric acid. Therefore, it can be expected that a new generation of lubricant formulations includes boron compounds. This paper presents an overview of various solid and liquid lubricants containing boron as an important ingredient, and is intended to aid the development of new lubricant

Design methodology for optical interconnect Topologies in NoCs with BER and transmit power constraints

Optical Network-on-Chip (ONoC) has emerged as an enabling technology to integrate a large number of processing cores in a single die. In this paper, we review some of the existing optical interconnect topologies for ONoCs and, propose a novel optical topology using multiple-segment buses (MSB) wherein several clusters of cores are interconnected in optical domain using MSB-based multiple optical interconnects. In particular, we analyze the bit-error rate (BER) performance of various ONoC topologies including the proposed MSB topology, taking into account signal losses and crosstalk components along the signal paths. The proposed MSB topology for 16 clusters offers an encouraging BER performance as compared to the other existing topologies, within the acceptable limit of per-wavelength launched power (1.5mW). The BER performance in 16-cluster MSB topology is further improved by incorporating forward error-correcting codes in the communicating clusters. Having studied the 16-cluster MSB topology, the size of the ONoC is scaled up to 64 clusters, wherein the 16-cluster topologies are used as modular MSB units (MUs), which are interconnected by inter-MU buses with optical-electronic-optical conversions at the exit and entry points from and into the communicating MUs. For 64-cluster modular MSB, the impacts of error-correcting codes are also examined. Finally, the paper provides a study on the impact of thermal mistuning of MRRs on the average BER of ONoCs, leading to a requirement of 20MHz laser linewidth to achieve an extinction ratio of 15dB for the ONoC setting considered in the study

Testing Network-on-Chip Communication Fabrics

Network-on-chip (NoC) communication fabrics will be increasingly used in many large multicore system-on-chip designs in the near future. A relevant challenge that arises from this trend is that the test costs associated with NoC infrastructures may account for a significant part of the total test budget. In this paper, we present a novel methodology for testing such NoC architectures. The proposed methodology offers a tradeoff between test time and on-chip self-test resources. The fault models used are specific to deep submicrometer technologies and account for crosstalk effects due to interwire coupling. The novelty of our approach lies in the progressive reuse of the NoC infrastructure to transport test data to the components under test in a recursive manner. It exploits the inherent parallelism of the data transport mechanism to reduce the test time and, implicitly, the test cost. We also describe a suitable test-scheduling approach. In this manner, the test methodology developed in this paper is able to reduce the test time significantly as compared to previously proposed solutions, offering speedup factors ranging from 2x to 34x for the NoCs considered for experimental evaluation

Essential Fault-Tolerance Metrics for NoC Infrastructures

International audienceFault-tolerant design of Network-on-chip communication architectures requires the addressing of issues pertaining to different elements described at different levels of design abstraction -- these may be specific to architecture, interconnection, communication and application issues. Assessing the effectiveness of a particular fault-tolerant implementation can be a challenging task for designers, constrained with tight system performance specifications and other requirements In this paper, we provide a top-down view of fault-tolerance methods for NoC infrastructures, and present a range of metrics used for estimating their quality. We illustrate the use of these metrics by simulating a few simple but realistic fault-tolerant scenarios

Design, synthesis, and test of networks on chips

For networks on chips to succeed as the next generation of on-chip interconnect, researchers must solve the major problems involved in designing, implementing, verifying, and testing them. This article surveys the latest NoC architectures, methods, and tools and shows what must happen to make NoCs part of a viable future

A flexible network-on-chip simulator for early design space exploration

ISBN : 978-1-4244-2920-2International audienceThe communication requirements of large multi-core systems are convened by on-chip communication fabrics generally referred to as networks-on-chip (NoC). We have designed a simulation environment that allows early exploration of the performance and cost parameters of network-on-chip communication architectures, which is able to handle arbitrary topologies and routing schemes. The simulator implements a flit-level message-passing mechanism and supports application data specified as input trace files or generated at run-time by synthetic traffic generators